Hardik Modi, Dharmendra Chauhan, Sagarkumar Patel, Vishva Gondalia, and Jayesh Khistariya 2024. DESIGN AND IMPLEMENTATION OF VEDIC MULTIPLIER ON SPARTAN-6 FPGA USING VERILOG HDL. International Journal of Advances in Soft Computing and Intelligent Systems (IJASCIS). 3, 2 (Jul. 2024), 209–225.