HARDIK MODI, DHARMENDRA CHAUHAN, SAGARKUMAR PATEL, VISHVA GONDALIA, AND JAYESH KHISTARIYA. DESIGN AND IMPLEMENTATION OF VEDIC MULTIPLIER ON SPARTAN-6 FPGA USING VERILOG HDL. International Journal of Advances in Soft Computing and Intelligent Systems (IJASCIS), [S. l.], v. 3, n. 2, p. 209–225, 2024. Disponível em: https://sciencetransactions.com/index.php/ijascis/article/view/13. Acesso em: 24 sep. 2025.