Hardik Modi, Dharmendra Chauhan, Sagarkumar Patel, Vishva Gondalia, and Jayesh Khistariya. “DESIGN AND IMPLEMENTATION OF VEDIC MULTIPLIER ON SPARTAN-6 FPGA USING VERILOG HDL”. International Journal of Advances in Soft Computing and Intelligent Systems (IJASCIS) 3, no. 2 (July 31, 2024): 209–225. Accessed September 24, 2025. https://sciencetransactions.com/index.php/ijascis/article/view/13.