DESIGN AND IMPLEMENTATION OF VEDIC MULTIPLIER ON SPARTAN-6 FPGA USING VERILOG HDL

Abstract

Vedic Mathematics can rapidly conduct a several arithmetic operations. The multiplier unit is an essential part of general purpose and digital signal processors that greatly influences the processing speed. The Urdhva-Tiryagbhyam, a technique from Vedic math that makes it simple to multiply given integers as well, is utilized in this study to initiate a high-speed multiplier architecture. To determine product of two numbers, utilize the vertical and crosswise approaches referred to as Urdhva-Tiryagbhyam. Applying traditional Vedic mathematics, the paper discusses the creation of 2x2, 4x4, 8x8, 16x16, and 32x32 bit  Vedic multipliers. The multipliers were synthesized and simulated using XILINX ISE Design Suite v.14.7 software. The multipliers were generated and defined using Verilog Hardware Description Language (VHDL).