Journal Article Open Access
DESIGN AND IMPLEMENTATION OF VEDIC MULTIPLIER ON SPARTAN-6 FPGA USING VERILOG HDL
By Hardik Modi, Dharmendra Chauhan, Sagarkumar Patel, Vishva Gondalia, Jayesh Khistariya
Abstract
Vedic Mathematics can rapidly conduct a several arithmetic operations. The multiplier unit is an essential part of general purpose and digital signal ...
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Year:
2024
Citation:
Hardik Modi, Dharmendra Chauhan, Sagarkumar Patel, Vishva Gondalia, Jayesh Khistariya. (2024). DESIGN AND IMPLEMENTATION OF VEDIC MULTIPLIER ON SPARTAN-6 FPGA USING VERILOG HDL. International Journal of Advances in Soft Computing and Intelligent Systems (IJASCIS), 3(2), 326-342. https://doi.org/
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